[RC5] Athlon core contribution

Jonas Maebe jonas.maebe at rug.ac.be
Fri Dec 6 18:12:57 EST 2002

On vrijdag, dec 6, 2002, at 17:46 Europe/Brussels, Stephen Garrison 

> This may be true but I think the fact that you knew two, and only two,
> 64-bit keys would be in a single register and knew how they would be

No. If you only process 32 bits per key at a time (which is what the 
rc5 algorithm requires if I remember correctly), you get 4 keys per 
register. You can't do anything with two 64 bit keys in one register 
because there are no 64 bit operations in the altivec instruction set. 
So unless the upper and lower 32 bit require exactly the same 
operations and if those operations are completely independent, which I 
doubt, then you could load the whole keys at once.

Read also <http://www.slashnet.org/forums/DCTI-20020928.html>, then 
you'll see that the dnetc staff themselves say that the keyrates for 
rc5-64 and rc5-72 will be more or less the same. The only problem they 
mention is that the 80x86 and compatibles may have a slight problem 
because they're so register starved, <quote> But probably other 
architectures, especially RISC ones, won't be so affected. </quote>


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