[RC5] Athlon core contribution

Stephen Garrison garrison at ChE.UDel.Edu
Fri Dec 6 11:46:45 EST 2002


This may be true but I think the fact that you knew two, and only two,
64-bit keys would be in a single register and knew how they would be
arranged within the register makes things much simpler than trying to
split sixteen 72-bit keys across nine 128-bit registers and keeping track
of which bits within each register correspond to each particular key. I
would expect that this overhead of keeping track of portions of keys would
be costly if not impossible and might require that only one key be in each
register, approximately halving the RC5-64 performance when going to
RC5-72.

On Fri, 6 Dec 2002, Jonas Maebe wrote:
> 
> Doesn't the rc5 altivec core use bitslicing, ie. it processes n bits of 
> (128/n) keys at once? (I don't know how big n is) Going to a larger 
> keysize still means that you need more iterations of course, but not 
> that you need massive changes (except maybe in scheduling those 
> iterations optimally). After all, altivec cannot handle vectors with 64 
> bit elements either (only 32, 16 and 8 bit ones are supported), so if 
> the whole key had to be handled at once, it wouldn't have worked for 
> rc5-64 either.
> 
> 
> Jonas

-- 
Stephen Garrison

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