[RC5] core questions
hedonist at win.co.nz
Wed Mar 13 18:20:53 EST 2002
Colin L. Hildinger wrote:
> As I recall, the K6 core chips don't have a hardware rotate, it was
> implemented with shifts. The K7 core and the P5 and P6 cores have hardware
> rotate. This is a useful instruction for RC5. Its usefulness elsewhere has
> been debated considerably on this list. :)
Yup, and the P7 doesn't have rotate right? Hence it's low rc5 scores,
or is that another issue?
> ----- Original Message -----
> From: "blitz" <blitz at macronet.net>
>>Interesting...I'm "assuming" AMD did add the necessary MMX sort of
>>instruction set by the time things got to say 233 mhz or so....I recall
>>they called it something different than MMX, but it was the same thing.
>>box I'm on rite now, is a 233 amd, and I know it supports the mmx stuff.
>>So despite mmx being a dud for video, it makes Dnet cores run
AMD k5 didn't have MMX
AMD k6 did
AMD K6-2 had MMX and 3dnow, which was simlilar in theory to SSE
AMD k7 had the above plus 3dnow-enhanced, and mmx-enhanced.
AMD K7-4 had a few more instructions which combined with 3dnow gave it a
full SSE implementaion.
AMD k8 (hammer) will have SSE-2
Cyrix 6x86 didn't have MMX
Cyrix 6x86MX did have MMX
Not sure what the newer Cyrix/VIA III chips have, or if what they sell
as a Cyrix III is actually the IDT samuel.
Whilst the p5-MMX chips might be faster with the core doing some MMX
work, that is not true in all cases. The different chips implement
things differently and what instructions can be combined with what, and
what penalties there are when mixing instructions varies between CPUs.
So i think for instance, that the MMX core is slower on a K6 than the
non MMX core.
A 233MHz amd is probably a K6, maybe a K6-2. (or an overcloced K5 with
nitrogen cooling :p)
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