[RC5] AMD X86-64 port

Décio Luiz Gazzoni Filho decio at revistapcs.com.br
Mon Apr 28 14:05:57 EDT 2003

Hash: SHA1

On Monday 28 April 2003 12:08, gentryj at gci.net wrote:
> As I understand it from having examined the RC5 algorithm...  the actual
> "crunching" is hardcoded to use 32 bit rotates.  On native 64 bit chips
> this is bad because, as someone already pointed out, it must call extra
> opcodes to handle the 32 bit operation.  However, AMD's 64 bit chip doesn't
> appear to be native 64....  (I'm still slightly confused about how they are
> claiming a 64 bit CPU can actually perform better at 32 bit
> applications?!?).

Of course the Hammer is a 64-bit CPU, there's no discussion about that. Why 
don't you consider the 16-bit performance of past x86 CPUs? Recall that they 
evolved from a 16-bit instruction set, as seen on the 8086/80286, to the 
current 32-bit instruction set.

Now unnecessary use of 64-bit code is of course going to slow things down in 
any architecture: your pointers take twice as much space, so do immediate 
constants, the cost of performing complex arithmetic (multiplication and 
division) grows very fast with the size of the operands, etc. For instance, 
the DIV instruction has a 39-cycle latency for 32-bit operands and 71-cycle 
latency for 64-bit operands. One of the forms of the IMUL instruction has a 
3-cycle latency for 32-bit operands and 5-cycle latency for 64-bit operands. 
And so on.

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