[RC5] RC5-72 progress

Elektron elektron_rc5 at yahoo.ca
Mon Aug 2 10:24:29 EDT 2004

On 2 Aug, 2004, at 01:21, Fuzzy Logic wrote:

> Be careful how you phrase that. RISC is simply "reduced instruction
> set computer" and can be used to describe processors such as that
> found in the S/390 (what I work on), and so not all RISC processors do
> what you suggest. In fact, I would venture to say that you are
> describing a capability usually associated with CISC.

Neither x86 or M65K support separate source/destination registers. RISC 
and CISC also lose their meaning when a CISC processor has 100-some 
instructions, while the successor RISC has over 200.

The only real difference between CISC and RISC is that CISC does things 
which are relatively expensive to implement (such as memory access in 
most instructions, and native support for binary-coded-decimal, and 
instructions up to 12 bytes long or so), while RISC tends not to. RISC 
platforms also tend to prefer aligned loads and stores (whereas the x86 
has one-byte instructions), and equal-sized instructions (e.g. 32 

Having different source and destination registers isn't hard to 
implement, since you have to access registers anyway (it also reduces 
data dependency stalls, so I can write very fast CRC code [1]), nor is 
branch if decrement non zero (which seems to have the same latency as a 
branch). It just requires more bits per instruction, and you free bits 
by not needing to access memory (and often get more bits per 
instruction anyway).

The PowerPC is called RISC but can load/store multiple words, byte 
strings, with byte-reversal, and with update. Most of these are allowed 
to take longer than corresponding simple instructions (though my 
experience is that they're faster).

- Purr

[1]. The fastest CRC code has few branches.

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