[RC5] RC5-72 G5 core
elektron_rc5 at yahoo.ca
Sun Oct 31 10:03:11 EST 2004
>> The G5 is simply slower per MHz/GHz than the G4. For some
>> applications, this is offset by the larger memory bandwidth, but rc5
>> doesn't care about that. Of course, the G5 also scales much better
>> MHz-wise than the G4.
> The G5 is actually slower than expected due to a higher lantency
> between dependant instructions (2 clock cycles vs 1 on G4).
And, IIRC, two instructions per clock instead of three (though this may
not matter much for AltiVec). And branch alignment thingies.
>>> Is there any optimization work in progress? Are there any plans at
>>> all for an improved G5 core?
>> I don't know. It's of course possible that there are ways to improve
>> the keyrate on the G5, but it would surprise me if you could ever get
>> a keyrate per MHz comparable to a G4.
> A G5 could be 30% faster at RC5, but that'd require a very complex
> piece of code to work around the latency issues mentionned above. By
> now, nobody was able to write this new core.
I dunno, very careful use of registers might be able to fix this. Or
preloading things from the cache.
The future is still in hardware cores, though =P
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