[RC5] Runtime optimization??
T_Wolf at gmx.de
Fri Mar 3 02:19:00 EST 2006
Actually, I don't think that 6% improvement would really cut a big piece of
the whole thing.
I remember the transition from Pentium III to Pentium 4 based Systems, where
one Instruction (was it the "Rotate") was changed from Hardware to Emulation
within the CPU which slowed dnetc down by roughly 25% on P4 at the same
clockspeed (given an 1.4 GHz example). Check the RC5 Calculator here
(http://www.distributed.net/~nerf/rc5calc.html) ... (ok, I know it doesn't
work atm, but I'm sure, Nerf will fix it).
So with Dual Core now available, Quad Core to be introduced by INTC 2007, I
think that a coding improvement of 6% won't do much. Maybe Intel Corp
decides to put that instruction back into the cpu or extra instruction come
with next generation CPU's... Dnetc speed can vastly improve over today's
performance. Which is great if you ask me, but that's just my 2 cents here.
t_wolf at d.net
> I wish I was a coder,but if someone is actually working right now to
> make the current cores 6% more faster than they are now,maybe we could
> eventually actually break the 1% done barrier in my lifetime or cut the
> time to finish to 10 years or less :P
> Bert O'Dell
> Benjamin Kaufman wrote:
> >Just 1% in the scope of distributed.net speed is huge.
> >1% more on a few thousand computers, is a lot.
> >6% more on a few thousand computers is years shaved off the project.
> >Benjamin 'thumper^' Kaufman
> >On 02/03/06, Elektron <elektron_rc5 at yahoo.ca> wrote:
> >>On 2006-03-01, at 23:20:29, Fugu wrote:
> >>>Why don't the cruncher cores compiled using fftw-like optimizations?
> >>>Assembly code may be slightly faster, but in needs to be remade for
> >>>every platform...
> >>Because there's someone willing to rewrite it for every platform. A
> >>lot of work is spent in squeezing out an extra 6%.
> >>I don't even understand the AltiVec core.
> >>- Me
> >>rc5 mailing list
> >>rc5 at lists.distributed.net
> >rc5 mailing list
> >rc5 at lists.distributed.net
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